1. Field of the Invention
The present invention relates to structures of a semiconductor device, and methods of making the same, and more particularly, to a recessed-gate transistor device having a dielectric layer with multi thicknesses.
2. Description of the Prior Art
As the size of semiconductor devices shrinks, the gate channel length decreases correspondingly. Consequently, a short channel effect may occur, resulting in problems in increasing the integration of the semiconductor devices and the operating performance.
The conventional method of solving the short channel effect includes decreasing the thickness of the gate oxide layer or increasing concentration of the dopants. These methods, however, may deteriorate the reliability of the devices and decrease the speed of transferring data.
To solve the above-mentioned problems, a recessed-gate transistor design or an extended U-shape device (EUD) is used in the semiconductor field to increase the integration of an IC, such as a DRAM, and elevate the operating performance.
The recessed-gate transistor has a gate insulation layer formed on sidewalls and the bottom surface of a recess etched into a substrate, where a conductive substance fills the recess, contrary to a planar gate type transistor having a gate electrode formed on a planar surface of a substrate. Therefore, the integration of the recessed-gate transistor can be increased.
FIG. 1 shows the sectional view of a prior art DRAM device. As shown in FIG. 1, a recessed-gate transistor device 110 and a deep trench capacitor 120 disposed adjacent to the recessed-gate transistor 110 constitute a DRAM cell. In FIG. 1, a deep trench capacitor 220, which is adjacent to the aforementioned DRAM cell and is a part of another DRAM cell, is also demonstrated.
The recessed-gate transistor device 110 includes a recessed gate 111, a source region 113, a drain region 114 and a gate dielectric layer 115. The recessed gate 111 is embedded in a gate trench 112 in the substrate 1100. The U-shaped channel 116 of the recessed-gate transistor device 110 is situated at the bottom of the gate trench 112. In addition, a bit line contact plug 140 is positioned on the source region 113.
The deep trench capacitor 120 includes a doped polysilicon 122 acting as a top electrode, a single-sided buried strap (SSBS) 126, a sidewall capacitor dielectric layer 123, a collar oxide layer 125 and a trench top oxide (TTO) 130. For the sake of simplicity, only the upper portions of the deep trench capacitor 120 are shown in the figures. It is understood that the deep trench capacitor 120 further comprises a buried plate acting as the bottom capacitor electrode, which is not shown.
The recessed-gate transistor device 110 is connected to a diffusion region 124 expanded from the SSBS 126 through the drain region 114.
The structures of the deep trench capacitors 120, 220 are substantially the same. The deep trench capacitor 120 and the deep trench capacitor 220 belong to different DRAM cells. In the same way, the deep trench capacitor 220 also includes a doped polysilicon 222, a single-sided buried strap (SSBS) 226, a sidewall capacitor dielectric layer 223, a collar oxide layer 225 and a trench top oxide (TTO) 230.
The aforementioned recessed-gate technology has some shortcomings, for, example, high capacitance forming between the gate and the drain region, or between the gate and the source region, and high gate induced drain leakage (GIDL) forming in a region indicated by a circle 150. Additionally, as the device is scaled down, the landing area, shown by A1, will be too small and lead to the fabricating problems. These problems may deteriorate the operating performance of the devices.